Efficient Implementation of NTRU Cryptography using Residue Number System

FPGA Implementation of Residue Number System Structures

In this paper we explore the feasibility of implementing Residue Number System (RNS) based DSP algorithms on Lookup table based Field Programmable Gate Arrays (FPGAs). In this process, Binary Decision Diagrams are used for logic representation, and a new minimizing algorithm for incompletely specified functions is introduced. A sample residue arithmetic based design is presented along with prom...

A FPGA pairing implementation using the Residue Number System

Recently, a lot of progresses have been made in software implementations of pairings at the 128-bit security level in large characteristic. In this work, we obtain analogous progresses for hardware implementations. For this, we use the RNS representation of numbers which is especially well suited for pairing computation in a hardware context. A FPGA implementation is proposed, based on an adapt...

An Efficient Oblivious Transfer Protocol Using Residue Number System

Because the t-out-of-n oblivious transfer (OT) protocol can guarantee the privacy of both participants, i.e., the sender and the receiver, it has been used extensively in the study of cryptography. Recently, Chang and Lee presented a robust t-out-of-n OT protocol based on the Chinese remainder theorem (CRT). In this paper, we use the Aryabhata remainder theorem (ART) to achieve the functionalit...

A residue number system implementation of real orthogonal transforms

High Performance Adder Using Residue Number System

The Residue Number System based on 2 n 2 k -1 moduli set is used in the proposed model. There are more number of moduli sets among them the above mentioned one is having high performance than the other. Adder is one of the key components for the application of Residue number system (RNS). Moduli set 2 n -2 k -1 where n=16 and k=14 with the form can offer excellent balance among the RNS channels...